This is an indicative list of topics related to the BrainFrame project. More topics in this context are often available. Contact us for more details on what is available.

 

1. Automating Python H/W Models for Brain Simulation

Topic:


FPGAs are increasingly used for accelerating brain-model simulation. However, existing FPGA-programming tools are cumbersome for neuroscientists to use.There is need for a familiar coding front-end for implementing brain models which could then be executed on fast FPGA-based platforms.

PyNN, a new, Python-based, simulator-independent language provides a common front-end (API) for various legacy neuromodeling software simulators such as NEURON and GENESIS. The PyNNframework is extensible with custom simulator back-ends, as demonstrated within the FACETS project (ASIC-based simulator).

In this work, we want to bring the benefits of two worlds together: (a) the ease of use (and established user base) of PyNN for modeling realistic brain models with (b) the staggering simulation speed that FPGA platforms can deliver in the field of brain simulation. As FPGA tools already exist, this thesis work will focus on implementing the “bridge” from the PyNN front-end to the FPGA back-end (already existent within the Neuroscience Dept. of Erasmus MC). In essence, a source-to-source (Python to C or VHDL) translation work is needed.

Expected effort:


The student is expected to study PyNN’s existing API’s as well as API’s made available through Xilinx Vivavo and/or High-Level-Synthesis tool and write either a simple source-to-source translator for (static) mapping of PyNN neural models to synthesizable-C or VHDL constructs, or establish inter-process communication between the API’s for (dynamic) mapping of PyNN models to a free-running, FPGA-based, brain-simulation engine.

Expected outcome:


Implementation of a high-level synthesis tool for implementing neural model simulation on FPGA-based platforms. The model employs PyNN to make the use of the tool natural to the neuroscience community. Exploration of the challenges of the creation of such a tool on a DFE machine and basic proof of concept implementation using the already implemented hardware libraries of the inferior olive model.

Prerequisites:


Students with skills in compiler design and inter-process communication will be preferred.

ContactGeorgios Smaragdos, Christos Strydis

 

2. A system for ultra-fast, two-way cognitive brain-machine interface

The activity of brain neural networks determines our cognitive processes. With modern methods, we can monitor the electrical activity of up to hundreds neurons, and decode its information content. In this way we are beginning to understand for example how memory works. At the same time, we now have a way of perturbing neuronal activity by using light. If we could detect complex neural patterns, decode them in real-time and disrupt them selectively, we would have a tool for “editing” memory and cognition and of understanding their mechanisms. In this project, we plan to extend an existing open-source, multi-channel, data-acquisition system to perform low-latency, online data analysis on a FPGA module and drive an array of stimulators. The intended system would be at the cutting edge of current neurotechnology, and may help to produce significant advances in brain research.

 

 

See above figure , for the overall system block diagram. Currently, closed-loop control is implemented at block (4) which is custom software running on a PC. Closing the loop this way is obviously very slow, typically taking up 10s to 100s of milliseconds – which is way to slow for real-time closed-loop control. We essentially want to migrate the algorithms running in block (4) (i.e. the PC) to the Xilinx Spartan FPGA residing in block (3) and effectively drive response times down to a few milliseconds or less. The FPGA already resides on a suitable dual-PCB system and all needed pinouts (analog and digital I/O) are working.

 

ContactGeorgios Smaragdos, Christos Strydis

 

 

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